Method and system for providing a digital signal representing an analog signal

ABSTRACT

A method for providing a digital output signal ( 59 ) representing an analog input signal ( 54 ) in a system ( 50 ) including an analog circuit ( 51 ) and a control unit ( 52 ). Analog circuit ( 51 ) preferably features high bandwidth, high gain, and low current consumption. Analog circuit ( 51 ) is preferably implemented with low accuracy components. Control unit ( 52 ) keeps error outputs ( 55 ) of analog circuit ( 51 ) at a minimal value so that control unit ( 52 ) cancels analog input signal( 54 ) by outputting discrete value signals ( 58 ) in a feedback loop as input ( 58 ) to analog circuit ( 51 ). A DSP ( 53 ) of system ( 50 ) is previously trained using known analog signals and a model relating inputs ( 54,58 ) to error outputs ( 55 ) of analog circuit ( 51 ) is previously known. During operation, a digital representation ( 57 ) of the discrete value signals ( 58 ) is fed to DSP ( 53 ) that reconstructs analog input signal ( 54 ) by knowing from the prior training the effect of control unit ( 52 ) and the model of analog circuit ( 51 ).

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a national phase application under 35 U.S.C.371 from international application PCT/IL2004/000739 filed on Aug. 11,2004 which has priority from US provisional application 60/494,575 filedon Aug. 13, 2003.

FIELD AND BACKGROUND OF THE INVENTION

The present invention relates to analog signals sampling and, moreparticularly, to method and corresponding device for sampling at leastone analog signal and providing digital representation thereof,featuring an analog circuit integrated with a control unit, wherein thecontrol unit is keeping error outputs of the system at a minimal value.The control unit is using discrete value signals that are digitally feedto a DSP that is reconstructing the at least one analog input signal.

The present invention is primarily directed to applications requiringhigh bandwidth with low current consumption, including but not limitedto applications of signal processing of analog sources in a variety ofapplications such as radar, imaging and analog front-end of wirelessmodem, including those using direct RF sampling.

The inputs to a previous art sampler are analog signal(s) and a clock orany other deterministic signal or signals. Previous art sampler is asystem containing linear components, non-linear components, amplifiers,and optionally, delay elements and decision elements that output bits asfunction of its input, such as comparators or small analog to digitalconverters of 2 bits. The previous art sampler is designed to provideaccurate conversion of each analog sample to its digital equivalent.Occasionally, the previous art sampler is calibrated in order tocompensate for the inaccuracy of its components. More specifically, thegains and offsets of the previous art sampler are modified in order toachieve digital representation of the sampled analog signals featuringbetter accuracy. Alternatively, the previous art sampler includescalibration of its output in the digital domain.

Prior art samplers are described by models featuring multiple stages,wherein each stage in the model is independent from all other stages. Inother words, models of prior art samplers are an aggregation of multiplemodels of each stage. Each stage in the model refers to specific voltageor current value that is measured in a specific time frame. Each stagetreats the specific value it receives as an input and provides itsresult to the next stage. Moreover, prior art stage is not dependent onprevious values.

SUMMARY OF THE INVENTION

In contrary to the previous art sampler, the method of the presentinvention does not disclose a sampler providing an accurate conversionof each analog sample to its digital equivalent, but the digital outputof the sampler disclosed in the present invention features usefulinformation from which the digital representation of the input analogsignal can be calculated. Moreover, the sampler disclosed in the presentinvention is not calibrated in order to compensate for the inaccuracy ofits components. More specifically, the gains and offsets of the samplerdisclosed in the present invention are not modified in order to achievedigital representation of the sampled analog signals featuring betteraccuracy.

In other words, the method of the present invention discloses an analogcircuit featuring high bandwidth, high gain, and low currentconsumption, wherein that analog circuit is implemented by low accuracycomponents. The analog circuit is integrated with a control unit. Thecontrol unit is keeping error outputs of the system at a minimal valueso that the total effect of the control unit is canceling the effect ofthe input signals. By knowing the effect of the control unit, the inputsignals can be approximated. The control unit is using discrete valuesignals. These discrete value signals are feed to a DSP that isreconstructing the input signal by knowing the effect of the controlunit.

In contrary to the various kind of previous art samplers, the sampler ofthe present invention is not made of sequence of separate stages,wherein each stage operates without memory and independently producesdiscrete value to the next stage. The sampler of the present inventionfeatures a unified model describing all the stages of the sampler.Moreover, in a case where it is useful to construct the sampler of thepresent invention from two or more stages, there are interconnections,and/or feedback or other dependencies between the various stages, whichmakes it necessary to use a unified model rather than independent modelfor each stage. Moreover, typically some or all of the stages modelsinclude the influence of previous values. Those novel interconnectionsbetween the models describing the sampler of the present invention areone of the reasons enabling the present invention to use the novelcircuits described below and achieve its high performances.

Implementation of the method and corresponding device of the presentinvention involves performing or completing selected functions and/ortasks and/or steps and/or operations manually, semi-automatically, fullyautomatically, and/or, a combination thereof. Moreover, according toactual instrumentation and/or equipment used for implementing aparticular preferred embodiment of the disclosed method andcorresponding device, several selected functions and/or tasks and/orsteps and/or operations of the present invention could be performed byhardware, by software on any operating system of any firmware, or acombination thereof. In particular, as hardware, selected functionsand/or tasks and/or steps and/or operations of the invention could beperformed by a computerized network, a computer, a computer chip, anelectronic circuit, hard-wired circuitry, or a combination thereof,involving a plurality of digital and/or analog, electrical and/orelectronic, components, operations, and protocols. Additionally, oralternatively, as software, selected functions and/or tasks and/or stepsand/or operations of the invention could be performed by a dataprocessor, such as a computing platform, executing a plurality ofcomputer program types of software instructions or protocols using anysuitable computer operating system.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is herein described, by way of example only, withreference to the accompanying drawings. With specific reference now tothe drawings in detail, it is stressed that the particulars shown are byway of example and for purposes of illustrative discussion of thepreferred embodiments of the present invention only, and are presentedin the cause of providing what is believed to be the most useful andreadily understood description of the principles and conceptual aspectsof the present invention. In this regard, no attempt is made to showstructural details of the present invention in more detail than isnecessary for a fundamental understanding of the invention, thedescription taken with the drawings making apparent to those skilled inthe art how the several forms of the invention may be embodied inpractice. Identical structures, elements or parts which appear in morethan one figure are preferably labeled with a same or similar number inall the figures in which they appear. In the drawings:

FIG. 1 is a schematic diagram illustrating the preferred embodiment ofthe generalized analog signals sampler of the present invention.

FIG. 2 is a schematic diagram illustrating an exemplary method foridentifying the model of the analog signals sampler of the presentinvention.

FIG. 3 is a schematic diagram illustrating an alternative exemplarymethod for identifying the model of the analog signals sampler of thepresent invention.

FIG. 4 is a schematic diagram illustrating the first multi-stageexemplary preferred embodiment of the generalized method andcorresponding analog signals sampler of the present invention.

FIG. 5 is a schematic diagram illustrating an exemplary implementationof a stage, in accordance with the multi-stage exemplary preferredembodiments of the generalized method and corresponding analog signalssampler of the present invention.

FIG. 5A is a schematic diagram illustrating an alternative division fora MIMO system in a stage.

FIG. 6 is a schematic diagram illustrating an alternative exemplaryimplementation of a stage, in accordance with the multi-stage exemplarypreferred embodiments of the generalized method and corresponding analogsignals sampler of the present invention.

FIG. 6A is a schematic diagram illustrating an alternative division fora MIMO system in a stage.

FIG. 7 is a schematic diagram illustrating the second multi-stageexemplary preferred embodiment of the generalized method andcorresponding analog signals sampler of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention relates to analog signals sampling and, moreparticularly, to method and corresponding device for sampling at leastone analog signal and providing digital representation thereof,featuring an analog circuit integrated with a control unit, wherein thecontrol unit is keeping error outputs of the system at a minimal value.The control unit is using discrete value signals that are digitally feedto a DSP that is reconstructing the at least one analog input signal.

The present invention successfully addresses shortcomings andlimitations of presently known methods for providing accurate conversionof analog sample to its digital equivalent, by being simpler, morerapid, and therefore, more cost effective, than currently usedtechniques for providing accurate conversion of analog sample to itsdigital equivalent. The method of the present invention is readilyimplemented using analog parts and digital parts. Analog parts areselected from: analog discrete parts, integrated circuit or RFcomponents. The digital parts are selected from: discrete digital parts,integrated digital parts, mixed signal ASIC, or separate analog anddigital ASICs. The digital part of the sampler of the present inventioncan also be implemented in a general purpose DSP or CPU. The generalpurpose DSP or CPU can be embedded, not embedded, or stand-alonecomputer (e.g. PC).

Moreover, the method and device of the present invention are generallyapplicable as a ‘stand-alone’ device for sampling analog signals andproviding digital representation thereof, or, as a component used incombination with other methods, devices, and systems, using the sampledanalog signals.

The present invention features a unique method, and a correspondingsampling device featuring high rate of sampling analog signals andproviding digital representation thereof, with low power consumption.For example, a sampler in accordance with the present invention mayconsume average current in the order of 5 mili-Ampere (mA) when samplingan analog input signal featuring bandwidth of 50 MHz. This is in strongcontrast to the previous art samplers consuming about 50-100 mA whensampling an analog input signal featuring the same bandwidth, when bothimplemented in the same device technology.

Another unique feature is that for high-speed signals the method of thepresent invention achieves better effective number of bits (ENOB),resulting in better precision, compared with the previous art samplers.This significant improvement is a result of the fact that the offsets,components inaccuracy, and unintentional delay in one clock wirerelative to other wires distributing the same clock, known as clockskew, can be described by the general linear model and compensated bythe adaptive algorithm described below.

Another unique feature of the method of the present invention is thehigh robust designing method, compensating all inaccuracies in theadaptive algorithm described below. Moreover, the sampler in accordancewith the present invention can be easily scaleable through geometrychanges in the technology of fabrication.

Still another unique feature of the sampler of the present invention isthat the assembling blocks of the sampler are well available in most ofthe common low cost digital CMOS commercial fabrication processes andtherefore do not require a special fabrication process and are easilyincorporated in a mixed signal chip containing also large and complexdigital blocks.

Still another unique feature of the sampler of the present invention isthe high usable amplitude range (dynamic range) of the analog inputsignal. The high dynamic range is achieved by the non-obvious structureof the sampler of the present invention, rarely found on previous artsamplers, designed such that the Signal to Noise Ratio (SNR) is almostindependent on the average signal power within the required dynamicrange. For example, an input analog signal featuring average RMS of 1mili volt (mV) may be sampled by the sampler of the present inventionwith SNR=48 dB, while feeding the same sampler with an input analogsignal featuring average RMS of 100 mV may also be sampled with SNR=48dB, given these two input analog signals feature the same statisticaldistribution.

Still another unique feature of the sampler of the present invention isthe ability to sample low power signals. This significant feature is aresult of the low self-noise of the sampler of the present invention.The low self-noise of the sampler of the present invention is a resultof its very low power operation, creating less noise contaminating theinput signal. Moreover, most of the noise created by the sampler of thepresent invention, contaminating the input signal or the intermediatesignals, can be incorporated into the model and compensated for.

Still another unique feature of the sampler of the present invention isits low price resulting from the very small footprint needed forimplementation, and the fact that the building blocks are simple,inaccurate, and consume low power.

It is to be understood that the present invention is not limited in itsapplication to the details of the order or sequence of functions and/ortasks and/or steps and/or operations or implementation of the method forsampling analog signals and providing digital representation thereof orto the details of construction, arrangement, and, composition of thecorresponding analog signals sampler thereof, set forth in the followingdescription, drawings, or examples. The present invention is capable ofother embodiments or of being practiced or carried out in various ways.Moreover, it is to be understood that the phraseology, terminology, and,notation, employed herein are for the purpose of description and shouldnot be regarded as limiting. Moreover, the method and correspondingsampler of the present invention can be implemented in a variety ofconfigurations, for example, Multi Input Multi Output (MIMO) system 51and control unit 52 illustrated in FIG. 1, may be of variableconfiguration, including, but not limited to, multi-stageimplementation, as illustrated for example in FIG. 4, or iterativeimplementation using one stage and feedback.

Throughout the following description and accompanying drawings there isfirst provided description of the preferred embodiment of thegeneralized method and corresponding analog signals sampler of thepresent invention, followed thereafter by detailed descriptions andillustrations of two different exemplary preferred embodiments of thegeneralized method and corresponding analog signals sampler of thepresent invention.

The preferred embodiment of the generalized method and correspondinganalog signals sampler of the present invention is illustrated inFIG. 1. The preferred embodiment of the generalized method andcorresponding analog signals sampler is readily extendable andapplicable to the following description of two exemplary preferredembodiments of the generalized method and corresponding analog signalssampler of the present invention.

The first exemplary preferred embodiment of the generalized method andcorresponding analog signals sampler of the present invention, relatesto a multi-stage type configuration of the sampler disclosed in thepreferred embodiment of the generalized method, whereby Multi InputMulti Output (MIMO) system 51 and control unit 52 are implemented in twoexemplary stages. Each stage features a MIMO systems and a controller,as illustrated in FIG. 4. It is to be understood that the multi-stagesampler in accordance with the present invention can be easily scaleablethrough duplications of its stages, as is well known in the art ofelectronic hardware design.

The second exemplary preferred embodiment of the generalized method andcorresponding analog signals sampler of the present invention, relatesto a similar multi-stage type configuration of the first exemplary set,but, here, there are plurality of multi-stage samplers sampling the sameanalog input signal, as illustrated in FIG. 7.

For each set of exemplary preferred embodiments, the multi-stage samplerin accordance with the present invention has a scalability capability toincrease its resolution through increasing the number of stages. It isto be understood that even though the resolution can be increasedunlimited, the actual ENOB is limited by noise and other factors.Therefore, adding additional stages, once the maximal SNR has beenachieved, does not improve performance, unless the dynamic range needsto be increased. The exemplary preferred embodiments illustrate twostages sampler, but it should be understood that a resolution of morebits is implemented with the addition of stages. In other words, itshould be understood that the sets of exemplary preferred embodimentsillustrate only two stages out of many more implemented in arepresentative exemplary sampling device in accordance with the presentinvention.

In the following description of the method of the present invention,included are only main or principal functions and/or tasks and/or stepsand/or operations needed for sufficiently understanding proper‘enabling’ utilization and implementation of the disclosed method anddevice for sampling analog signals and providing digital representationthereof. Accordingly, descriptions of the various required or optionalminor, intermediate, and/or, sub functions/tasks/steps/operations, whichare readily known by one of ordinary skill in the art, and/or, which areavailable in the prior art and technical literature relating to thefield of sampling analog signals, are not included herein.

Functions and/or tasks and/or steps and/or operations and/or,components, and/or implementation of the method and corresponding devicefor sampling analog signals and providing digital representationthereof, according to the present invention, are better understood withreference to the following description and accompanying drawings.

The preferred embodiment of the generalized method for sampling analogsignals and providing digital representation thereof, in accordance withthe present invention, is described herein. Referring now to thedrawings, FIG. 1 is a schematic diagram illustrating the preferredembodiment of the generalized analog signals sampler of the presentinvention.

In FIG. 1, the device for sampling at least one analog signal andproviding digital representation thereof, hereinafter, referred to assampler 50, features the following primary components: (a) Multi InputMulti Output (MIMO) system 51, (b) control unit 52, and (c) DigitalSignal Processor (DSP) 53. It is to be understood that all materialdisclosed hereinafter is only representing the main and important partsof the method for sampling analog signals and providing digitalrepresentation thereof and may be executed in parallel hardware design.

In the preferred embodiment of the generalized method of the presentinvention there is feeding Multi Input Multi Output (MIMO) system 51with at least one analog input signal 54 and discrete correction signals58.

At least one analog input signal 54 is the analog signal to be sampledand digitally represented by sampler 50 as digital output 59. The atleast one analog input signal 54 and discrete correction signals 58 arefed to MIMO system 51.

There is MIMO system 51 providing analog monitoring outputs 55 beingrelated to the at least one analog input signal 54 and discretecorrection signals 58.

MIMO system 51 is characterized by the fact that, at leastapproximately, the relationship between one or more of MIMO system inputsignals (54 and 58) to MIMO system analog output signals 55 can bedescribed by a model. Moreover, the model of MIMO system 51 ischaracterized by the fact that it cannot be easily separated intoindependent stages. Moreover, the model of MIMO system 51 ischaracterized by the fact that it cannot be broken into separateindependent stages which processes one sample each time, without usingmemory from previous operations.

Alternatively, MIMO system 51 is characterized by the fact that therelationship between one or more of MIMO system input signals (54 and58) to MIMO system analog output signals 55 can be described by a modelhaving practical accurate identification algorithm. Analog outputsignals 55 of MIMO system 51 are analog signals that are used formonitoring the state of MIMO system 51 and therefore referred tohereinafter as analog monitoring outputs 55.

It is to be understood the model describing the MIMO system can haveother equivalent or similar formulations without affecting thegeneralization of the present invention. Moreover, the model describingthe MIMO system is not limited to the relationship between one or moreof MIMO system input signals (54 and 58) to MIMO system analog outputsignals 55, and may include other parameters as needed.

MIMO system 51 features a combination of components selected from thegroup of: linear components (with or without memory), non-linearcomponents (with or without memory), amplifiers, and delay elements.Optionally, operation of MIMO system 51 depends on a synchronizationclock 56 that may be a signal featuring fixed pulse shape and frequency,or any other deterministic signal featuring frequency.

It is to be emphasized, that even in the case that operation of MIMOsystem 51 is time varying and thus depends on a synchronization clock56, the MIMO system 51 operates on signals that are analog and timecontinuous. Moreover, MIMO system 51 outputs signals that are analog andtime continuous. Hereinafter such a MIMO system is referred to as a“continuous MIMO”.

There is feeding control unit 52 with analog monitoring outputs 55 and asynchronization clock 56.

Synchronization clock 56 may be a signal featuring fixed pulse shape andfrequency, or any other deterministic signal or signals featuringfrequency.

In an exemplary embodiment of the present invention, synchronizationclock 56 is used for timing some or all of the outputs of control unit52. The outputs of control unit 52 are discrete correction signals 58and digital representation of the discrete correction signals 57.

There is control unit 52 implementing a negative feedback control loopby feeding MIMO system 51 with discrete correction signals 58, in orderto keep at least one of the analog monitoring outputs 55 to be within adeterministic or probabilistic set of predefined constraints.

For example, control unit 52 is keeping at least one of the analogmonitoring outputs 55 within a predefined desired range, or having a lowpower.

The discrete outputs of control unit 52, referred to as discretecorrection signals 58, connected to MIMO system 51, can take a valueselected from a set of few values, or alternatively a waveform selectedfrom a set of waveforms. Preferably, the set of few values is determinedsuch that the control unit can do its job optimally. In an exemplaryembodiment, discrete correction signals 58 and the at least one analoginput signal 54 may be either voltages pulse or currents pulse.Moreover, each one of the discrete correction signals 58 may take avalue selected from its own set of values.

Control unit 52 is characterized by the fact that, at leastapproximately, the relationship between analog monitoring outputs 55 todiscrete correction signals 58 can be described by a model.

It is to be understood the model describing control unit 52 can haveother equivalent or similar formulations without affecting thegeneralization of the present invention. Moreover, the model describingcontrol unit 52 is not limited to the relationship between analogmonitoring outputs 55 to discrete correction signals 58, and may includeother parameters as needed.

Control unit 52 features a combination of components selected from thegroup of: linear components (with or without memory), non-linearcomponents (with or without memory), amplifiers, delay elements,decision elements which output bits as function of its input, such ascomparators or analog to digital converters, digital to analogconverters, and processing elements.

There is control unit 52 feeding DSP 53 with digital representation ofthe discrete correction signals 57

Due to MIMO system 51 that, at least approximately, having a modeldescribing the relationship between one or more of MIMO system inputsignals (54 and 58) to MIMO system analog output signals 55, the digitalrepresentation of discrete correction signals 57 combined with the modelof MIMO system 51 featuring useful information describing the at leastone analog input signal 54.

There is DSP 53 receiving digital representation of the discretecorrection signals 57 and, occasionally or within a continuous trainingperiod, DSP 53 is identifying the model of sampler 50 for creating aninternal representation of the relationships between digitalrepresentation of the discrete correction signals 57 to one or more ofMIMO system input signals (54 and 58). The model of sampler 50 isinfluenced from the model of MIMO system 51 and the model and functionof control unit 52.

In an exemplary embodiment of the present invention, instead of having aseparate training period, the operation of the sampler alternatesbetween training and sampling, such that the input signal iscontinuously sampled, but with speed penalty.

In an exemplary embodiment of the present invention, sampler 50 is timeinvariant, or features small enough variation, or can be made almosttime invariant by using analog or digital compensation methods such asthe gain compensation described below. In this exemplary embodiment, themodel of sampler 50 can be assumed known, though typically with lowaccuracy. In a case where the application using the results of sampler50 does not demand higher accuracy, no training is necessary.

The identification process of the model of sampler 50 may be doneaccording to one of the following five exemplary identificationprocesses:

In the first exemplary identification process there is: (a) feedingknown analog signal or signals to the at least one analog input signal54 in a training period, (b) DSP 53 is reading digital representation ofthe discrete correction signals 57, (c) DSP 53 is identifying the modelof sampler 50 by applying system identification algorithm, based on theknown analog signal or signals at the at least one analog input signal54, and the digital representation of the discrete correction signals57. For example, well known in the art non-linear models identificationalgorithms based on known inputs are neural networks and Volterraseries. An exemplary reference book is: Adaptive Wireless Trancievers byL. Hanzo, C. H. Wong, M. S. Yee, Wiley ISBN 0470-84689-5.

It is noted that the method of the present invention may not guaranteesuccess in identification of every arbitrary MIMO system and controlunit The MIMO system and control unit of the present invention should beselected in a way leading itself to a one to one identification.Moreover, the identification process may not identify the transferfunction of sampler 50 explicitly, but identify only a relation betweenthe digital correction signals and the input signals.

The known analog signal or signals fed to the at least one analog inputsignal 54 may be produced by feeding known digital signals to a digitalto analog converter, driving the at least one analog input signal 54, asillustrated in FIG. 2. Referring to FIG. 2, training generation unit 61is feeding known digital signals to a digital to analog converter 60 andto DSP 53. An exemplary way of using sampler 50 on a continuous signalwithout disrupting its operation when feeding the known analog signal orsignals to the at least one analog input signal 54 in a training periodis using more than one sampler 50 and alternating between the samplerseach time one of the samplers is trained.

In the second exemplary identification process, whenever there isa-priori statistical knowledge of the at least one analog input signal54, the model of sampler 50 may be identified by applying anidentification algorithm that is using the a-priori statisticalinformation without requiring the training periods. In an exemplaryembodiment, assuming sampler 50 is linear, for pulse amplitudemodulation (PAM) input signal, the model of sampler 50 may be identifiedby applying an identification algorithm derived from the well knownBusgang algorithms. An exemplary reference book is: Adaptive FilterTheory by Simon Haykin, Prentice Hall, N.J., ISBN 0-13-013236-5. Inanother exemplary embodiment, assuming sampler 50 is non-linear, forpulse amplitude modulation (PAM) input signal, the model of sampler 50may be identified by applying neural networks identification algorithms.

In the third exemplary identification process, whenever the sampler isenclosed in a system performing several signal processing functions, andthat system contains some information regarding the at least one analoginput signal 54, that information may be sufficient for enabling anidentification algorithm of the model of sampler 50, without requiringthe training periods. Some exemplary systems performing several signalprocessing functions that may contain some information regarding the atleast one analog input signal 54 are: modem, pulse shaper, equalizer,down converter, decoder, and demodulator.

In the fourth identification process, as illustrated in FIG. 3 wheneveran additional MIMO subsystem 62 having a system model with unknownparameters, is used for identifying the model of sampler 50, unknownparameters of both systems can be identified by joint modelidentification by using training generation unit 61 that is feedingknown digital signals to MIMO subsystem 62 and to DSP 53

In the fifth identification process, analog input signal 54 is not usedfor training, and training is achieved by toggling some of the discretecorrection signals 57 in a sequence generated by the DSP, and lettingthe control unit calculating the rest of the discrete correction signals57. Applying an identification algorithm, for example LMS, can be usedfor identifying the model of sampler 50.

There is periodically repeating the identification process of the modelof sampler 50 in order to update the model parameters.

Due to environmental changes, there is a need to periodically repeat theidentification process of the model of sampler 50 in order to update themodel parameters. Whenever sampler 50 is time invariant, there is noneed to periodically repeat the identification process of the model ofsampler 50 in order to update the model parameters.

Whenever the model of MIMO system 51 or the model of control unit 52 istime invariant, there is no need to periodically repeat theidentification process of the model of sampler 50 in order to update themodel parameters, but only repeat the identification process of the timevariant model.

Whenever the model of control unit 52 is known a-priori, there is only aneed to identify the model of MIMO system 51.

It is to be understood that without losing generality, the model ofsampler 50 can be the inverse model describing the relationships betweendigital representation of the discrete correction signals 57 to one ormore of MIMO system input signals (54 and 58), or alternatively, a modeldescribing the relationships between one or more of MIMO system inputsignals (54 and 58) to digital representation of the discrete correctionsignals 57. In the last case, there is a need to inverse the model inorder to reconstruct digital output signal 59.

There is DSP 53 calculating, or implicitly using in further processing,digital output signal 59 by using: digital representation of thediscrete correction signals 57, the model of sampler 50, and thedeterministic or probabilistic set of predefined constraints onmonitoring outputs 55, wherein digital output signal 59 represents theat least one analog input signal 54.

DSP 53 is reconstructing digital output 59 (representing the at leastone analog input signal 54) using digital representation of the discretecorrection signals 57, the deterministic or probabilistic set ofpredefined constraints on monitoring outputs 55, and the model ofsampler 50 (representing the relationship between input signals 54 and58 to digital representation of the discrete correction signals 57).

In an exemplary embodiment of the present invention, digital outputsignal 59 is not explicitly reconstructed, but the reconstruction iscombined with subsequent signal processing functions. For example, whenan equalizer is applied to the signal, the equalizer can be combinedwith the model of sampler 50 and directly applied to digitalrepresentation of the discrete correction signals 57.

In an alternative exemplary embodiment, only a partial reconstruction isneeded. For example, when only the sign of analog input signal 54 isrequired, it is enough to partially reconstruct analog input signal 54by applying a simpler and less complex method featuring preservation ofthe sign information.

In an exemplary embodiment of the present invention, MIMO system 51 islinear MIMO system having few inputs and few outputs. One or more of theinputs are connected to the input signals to be sampled and the rest arecontrol inputs connected to the output of a control unit. The controlunit has discrete outputs connected to the control inputs of the linearMIMO system. Each one of the discrete outputs can take one of a set offew values. For example, the digital corrections can be a selectionbetween two constants K1 and K2, or K or −K, wherein ‘K’ denotes apredefined value. Moreover, each control output can have its own set ofvalues.

Hereinafter analyzed system featuring one input signal to be sampled.The gain of an output, denoted by Yj, relative to an input, denoted byXi, of the linear MIMO system is defined as the square root of the powerat the output to the power at the input:

${gain} = \sqrt{\frac{P({Yj})}{P({Xi})}}$where ‘P’ denotes average power. It is to be understood that thedefinition of the gain can have other equivalent or similar formulationswithout affecting the generalization of the present invention. The gainis measured by feeding linear MIMO system with an analog test signal atinput Xi and measuring the power of the analog test signal at thedesired output Yj, while: (a) all the inputs of linear MIMO system areset to zero (including the control inputs), (b) the Xi analog testsignal is small enough so that any point within the system is within thelinear range, (c) the Xi analog test signal features the same propertiesas typical analog signal at the input of the sampler, and in particular,features the same spectral properties and amplitude distribution astypical analog signal at the input of the sampler, although the testsignal may have smaller amplitude.

Amax is defined as the maximum gain among all the gains of thecontrolled outputs of the linear MIMO system, in relation to analoginput 54. The corresponding output is called the ‘maximum gain output’.As disclosed below, the gain Amax is related to the number of equivalentbits of the analog signals sampler accuracy by:

$\frac{A\;{\max \cdot \sqrt{P\left( {{Xm}(t)} \right)}}}{\sqrt{P\left( {{Yj}(t)} \right)}} \propto 2^{({{Number}\mspace{14mu}{of}\mspace{14mu}{equivalent}\mspace{14mu}{bits}})}$

Wherein, Yj denotes the maximum gain output, Xm(t) denotes the sampledinput with the maximum allowed power to be fed to the analog signalssampler, while the sampler is working properly, i.e. the sampler is ableto control the controlled outputs. For such a sampler to be useful, thenumber of equivalent bits of the sampler as computed by just describedformula should be as high as possible.

The just described sampler provides digital representation of the analoginput signal since the system is linear, the signal at the maximal gainoutput Yj(t) is the sum of the signals passed through the system andeach correction sequence, entered in the control inputs, passing throughthe system. Each signal passing through the system is gaining gain ofapproximately Amax, and also feature some distortion, denoted byf(x(t)), where f is a linear distortion.Yj(t)=r(t)+A max·f(x(t))

By passing both sides of the equation through the inverse response of: Amax·f (x(t)), we get:

$\frac{f^{- 1}\left( {Y_{j}(t)} \right)}{A\;\max} = {{\frac{f^{- 1}\left( {r(t)} \right)}{A\;\max} + {x(t)}} = {e(t)}}$

Wherein, r(t) denoted the sum of the responses of the system to thecorrection sequences, and the error signal, denoted by e(t), is boundedif Yj(t) is bounded, or the power of the error signal is bounded if thepower of Yj(t) is bounded, assuming f(t) is not considerably changingthe amplitude or power, respectively.

As a conclusion, reconstructing

$\frac{f^{- 1}\left( {r(t)} \right)}{A\;\max}$in DSP 53 resulting in digital representation of the signal x(t) withmax error equal to the range of Yj(t) divided by Amax. It is noted thatthe function ‘f’ might not be invertible. Since it is desirable toreconstruct a sampled version of x(t) and not x(t) itself, it issufficient to reconstruct the sampled version of x(t), and therefore togenerate only

$\frac{f^{- 1}\left( {r(t)} \right)}{A\;\max}$at the sampling times.

Using the control unit for minimizing or bounding the monitor outputs orthe monitor outputs power, and designing the MIMO system withsufficiently large Amax, should decrease the error of the reconstructedsignal. As a conclusion, above described analog signals sampler doeswell represent the analog signal.

It is to be understood that sampler 50, featured components, anddifferent positions of thereof, as illustrated in FIG. 1, is only arepresentative of the method and device for sampling analog signals andproviding digital representation thereof, of the present invention.Multi Input Multi Output (MIMO) system 51, control unit 52, and DSP 53,may be of variable configuration, including, but not limited to,multi-stage implementation and feedback iterative implementation.Moreover, MIMO system 51 can be linear or nonlinear. For example, FIG. 4illustrates a multi-stage configuration of sampler 50 constructed andoperative for sampling at least one analog input signal 54 and providingdigital representation 59 thereof, in accordance with the followingaccompanying method and corresponding device of the present invention.Moreover, multi-stage configuration including an iterative control mayreduce the complexity of the control function by transferring theresidual error to subsequent stages in each stage where the controlfunction is successfully implemented. Moreover, the multistagearchitecture is highly scalable since additional stages or units can beeasily added.

It is to be clearly understood that above described sampler 50 isextendable and applicable to the following description of exemplarypreferred embodiments of the generalized method, along withcorresponding exemplary preferred embodiments of the generalized analogsignals sampler device, of the present invention, as described herein.

Herein described the first multi-stage exemplary preferred embodiment ofthe generalized method and corresponding analog signals sampler of thepresent invention. The first multi-stage exemplary preferred embodiment,as illustrated in FIG. 4, relates to a multi-stage type configuration ofthe sampler disclosed above in the preferred embodiment of thegeneralized method. The multi-stage type sampler configuration featuringa plurality of stages, each stage producing an analog monitoring outputand digital representation of the discrete correction signals. A digitalrepresentation of analog input signal 54 can be obtained from theidentified model of the sampler and the digital representation of thediscrete correction signals produced by each stage.

Referring to FIG. 4 compared with FIG. 1, MIMO system 51 and controlunit 52 are implemented in two stages (73 and 74) sampler configuration,generally noted 75, wherein an analog signal is passed through stages 73and 74. It is to be understood that FIG. 4 illustrates schematically atwo stage configuration of a multi-stage sampler in accordance with thepresent invention. The multi-stage sampler in accordance with thepresent invention is scale through duplications of stages 73 and/or 74,as is well known in the art of electronic hardware design. MIMO system51 is implemented in FIG. 4 by MIMO systems 67 and 70. Control unit 52is implemented at FIG. 4 by controllers 68 and 71. Analog monitoringoutputs 55 are outputs 63 and 64. Discrete correction signals 58 arediscrete correction signals 65 and 66. Digital representation of thediscrete correction signals 57, are digital representation of thediscrete correction signals 78 and 79. It is to be understood that allthe disclosed method hereinafter only represents the main and importantparts of the method for multi-stage sampling analog signals andproviding digital representation thereof. Hereinafter disclosed methodis preferably executed in parallel hardware design.

In the first set of exemplary preferred embodiments of the generalizedmethod and corresponding analog signals sampler of the present inventionthere is, for each stage of sampler 75, except the first stage 73, MIMOsystem 70 receiving analog input signal 76 from the preceding stage anddiscrete correction signals 66 from its controller 71. MIMO system 67 ofthe first stage 73 receiving discrete correction signals 65 and analoginput signal 54 to be sampled and digitally represented by sampler 75 asdigital output 59. It is to be understood that each stage, whenconstructing sampler 75 from multi-stage elements, can be described as ageneral network multi-port device that its output is not only functionof its input, but also function of the rest of the circuit it isconnected to. The generation of a unified model from the separate stagesdescription as multi-port electrical device is well known part of theelectrical networks theory.

Analog input signal 54 is the analog signal to be sampled and digitallyrepresented by sampler 75 as digital output 59.

There is, for each stage of sampler 75, MIMO system (67, 70) providinganalog monitoring output (63, 64) being related to the input signals (54and 65; 76 and 66), and optionally to some of or all of the rest signalsin the system.

In an exemplary embodiment of the present invention, MIMO system (67,70) of each stage is characterized by the fact that, at leastapproximately, the relationship between MIMO system input signals (54and 65, 76 and 66) to MIMO system analog monitoring output signal (63,64) can be described by a model. Alternatively, MIMO system (67, 70) ofeach stage is characterized by the fact that the relationship betweenMIMO system input signals to MIMO system analog monitoring output signalcan be described by a model having practical accurate identificationalgorithm. MIMO system analog monitoring output signal (63, 64) is ananalog signal that is used for monitoring the state of MIMO system (67,70). It is to be understood that each analog monitoring output signalmay be composed of a single signal or plurality of signals.

Alternatively, although in this embodiment the MIMO system is composedof several stages, MIMO system is characterized by the fact that itsmodel is not made of an aggregation of multiple models of each stage.Sampler 75 features a unified model describing all of its stages.Moreover, in a case where it is possible to split the model of sampler75 to two or more models, there are interconnections between the modelsand some or all of the models may remember previous values.

MIMO system (67, 70) including a combination of components selected fromthe group of: linear components, non-linear components, amplifiers, anddelay elements.

In an exemplary embodiment of the present invention, synchronizationclock 56 is applied to sampler 75. Synchronization clock 56 is used forgenerating time varying response of MIMO system which is oftenadvantageous to the ability of generating the desired response, and forthe control unit to generate correction that can be easily converted todigital representation and feeding to the DSP.

There is, for each stage of sampler 75, controller (68, 71) receivinganalog monitoring output signal (63, 64) and a synchronization clock 56.

Synchronization clock 56 may be a signal featuring fixed pulse shape andfrequency, or any other deterministic signal or signals featuringfrequency. As described in the general embodiment of the presentinvention, synchronization clock 56 is used for timing some or all ofthe outputs of controllers 68 and 71.

In an exemplary embodiment of the present invention, the controller isusing information from previous stages and/or later stages in order toa-priori prepare a correction to the signal entering the current stage.Moreover, a-priori correction to the signal entering the current stagecan compensate for a delay in the controller operation. Moreover,information from previous stages and/or later stages can be used forbetter estimating the state of the current controlled MIMO system. Theinformation from previous stages and/or later stages can be receivedfrom analog monitoring output signal (63, 64). Optional dotted line 76is a schematic illustration of receiving analog monitoring output signalinformation from a previous stage.

There is, for each stage of sampler 75, controller (68, 71) providingdiscrete correction signals (65, 66) used for minimizing the value ofthe analog monitoring output (63, 64), and providing digitalrepresentation of the discrete correction signals (78,79).

Similarly to the preferred embodiment of the generalized method of thepresent invention, the object of the negative feedback control loopcontrol is keeping the analog monitoring outputs within a predefineddesired range.

The discrete outputs of control unit (68, 71), referred to as discretecorrection signals (65, 66), performing a negative feedback controlloop, can take one of a set of few values. Moreover, each one of thediscrete correction signals (65, 66) may have its own set of values.Discrete correction signals (65, 66) and the analog input signals (54,76) may be either voltages or currents. The controllers are using anegative control loop in order to control the analog monitoring outputsand keep the analog monitoring in a bounded range or in a bounded poweror any other predefined criterion.

Controllers (68, 71) including a combination of components selected fromthe group of: linear components (with or without memory), non-linearcomponents (with or without memory), amplifiers, delay elements,decision elements which output bits as function of its input, such ascomparators or analog to digital converters, digital to analogconverters, and processing elements.

There is each stage of sampler 75 producing the analog input signal (76,77) to the following stage.

In the last stage 74 of the multi-stage type configuration of thesampler of the present invention, there may be no need to implement thenegative feedback control loop because there is no need to produceanalog input signal 77, although it may be used for accuracy check.

It is to be understood that for all above described exemplaryimplementations (illustrated in FIG. 5 and FIG. 6), the discretecorrection signal can be fed back to the same cell for severaliterations, or can be fed to any subsequent cell for several iterations.Moreover, the division to MIMO systems is only a logical division thancan be done in additional alternative ways, all of them incorporated inthe scope of the present invention. Alternative divisions areillustrated in FIG. 5A and FIG. 6A by reference numerals 91 and 92.Moreover, MIMO system can be implemented by a sample & hold circuitinstead of above described capacitor and resistor without affecting thescope of the present invention.

There is DSP 53 receiving and storing digital representation of thediscrete correction signals (78,79) of each stage of sampler 75.

As is well known in the art of electronic hardware design DSP 53 isstoring the digital representation of the discrete correction signals(78,79) of each stage of sampler 75 in the appropriate memory referringto each analog input signal 54 to be sampled.

There is occasionally DSP 53 approximately identifying the model ofsampler 75, by identifying the unknown parameters within sampler 75, forcreating an internal representation of the relationship between digitalrepresentation of the discrete correction signals (78,79) to analoginput signal 54.

The model of sampler 75 is influenced from the model of MIMO systems 67and 70, and the model of control units 68 and 71. The identificationprocess of the model of sampler 75 may be done similarly according toone of the identification processes described in the preferredembodiment of the generalized method of the present invention.

There is periodically repeating the identification process of the modelof sampler 75 in order to update the model parameters.

Similarly to the disclosure at the preferred embodiment of thegeneralized method of the present invention, due to environmentalchanges, there is a need to periodically repeat the identificationprocess of the model of sampler 75 in order to update the modelparameters. Whenever sampler 75 is time invariant, there is no need toperiodically repeat the identification process of the model of sampler75 in order to update the model parameters.

Whenever the model of MIMO systems or the model of control units is timeinvariant, there is no need to periodically repeat the identificationprocess of the model of sampler 75 in order to update the modelparameters, but only repeat the identification process of the timevariant model.

Whenever the model of the control units is known a-priori, there is onlya need to identify the model of MIMO systems (67,70).

It is to be understood that without losing generality, the model ofsampler 75 can be the inverse model describing the relationships betweendigital representation of the discrete correction signals (78,79) toanalog input signal 54, or alternatively, a model describing therelationships between analog input signal 54 to digital representationof the discrete correction signals (78,79). In the last case, there is aneed to inverse the model in order to reconstruct digital output signal59.

Due to environmental changes, there is a need to periodically repeat theidentification process of the model of sampler 75 in order to update themodel parameters. Similarly to the preferred embodiment of thegeneralized method of the present invention, whenever sampler 75 is timeinvariant, there is no need to periodically repeat the identificationprocess of the model of sampler 75 in order to update the modelparameters.

In an exemplary embodiment of the present invention, MIMO systems arelinear systems. Herein an example of identifying, by DSP 53, the modelof the analog signals sampler when MIMO systems are linear systems.

There are various parameters that can change over time and environmentalconditions in the sampler of the present invention. For example, thegain applied to the analog input signal at a specific stage (73, 74) isdenoted as ‘alfa’ of that specific stage. The exact values of alfa and Kparameters in the various stages is unknown. Moreover, there areparasitic influences of each stage on the neighboring stages, and clockduty-cycle variation. Just described inaccuracies affect thecoefficients of the identified model of the sampler, but do not affectthe linearity of the system (i.e. the system is still a linear system).The coefficients of the linear model may be estimated by standardtechniques. In an exemplary embodiment, the coefficients of the linearmodel are estimated by the standard LMS technique, described below.

A known signal is injected by a digital-to-analog converter to theanalog input of the sampler when the sampler is not in use. A randomnon-correlated signal is inserted at the input. The randomnon-correlated signal features amplitude having the range of the maximuminput analog signals to the analog signals sampler of the presentinvention. The input and output bits are substituted into the LMS updateequation. Inter-stage-interference (ISI) should be estimated too whenexisting.

Random input is denoted by t(i), output vector (bits of the controlunit, aligned in time such that all bits of v(i) relates to the inputsample t(i)) is denoted by v(i), ‘c’ is the vector of coefficientsneeded to be estimated, ‘e’ is the error of the reconstruction of theinput, and ‘B’ is the number of stages of the sampler. Whenever thestages feature output of one bit, the length of the vectors c and v isequal to B. ‘mu’ is a small coefficient controlling the rate ofadaptation as is well known in the art of the LMS algorithms.

Each update of the LMS update equation is:e=c′·v(i)−t(i)c=c−mu·e·v(i)

The input signal is calculated as follows:x(i)=c′·v(i)

Above training can be implemented on prior art sampler havingindependent stages without ISI. Such model estimation can be moreaccurate than the recursive stage by stage estimation that is commonlyused in the field of the invention.

In an exemplary embodiment featuring ISI and DC component in the model,the LMS update equation becomes:e=trace(C′·V)−t+dC=C−mu·e·Vd=d−mu−e

‘C’ is a matrix BxP where ‘P’ is the ISI length. ‘V’ is a matrix BxPwith v(i−P+1+q) to v(i+q) as columns, where q is a time offset thatmight be needed to cover all post-cursor and precursor ISI terms. ‘d’ isthe DC term. trace( ) is the trace of the matrix.

The input signal is reconstructed by:x(i)=trace(C′·V)+d

In order to save complexity in above described calculation, some of theentries of C that are observed to be small enough are set to zero.

In another or additional exemplary embodiment, featuring inaccurateparameters in the system, there is a need for adaptive adjustment of thegain as disclosed herein. In the system described in FIG. 5, a gain ofslightly less than two is leading to stable system. There are systemsthat desire even lower gains to stay stable. For example, when thecontrol unit features a delay and the correction output is applied tolater stage, the gain should be substantially lower than two. However, again too low is leading to precision loss in the representation of thereconstructed analog signal.

In is noted that whenever the analog signals sampler is not stable,there is no point of performing the model estimation. When the analogsignals sampler is stable, there is a time consuming possible operationof estimating the parameters of the sampler using for example the LMS,then calibrating the system, and then estimating the parameters again.An improved operation, that is not a replacement for the LMS since it isnot accurate, but can be used for inserting the gain in its desiredrange is: if there is N1 ‘1’s or ‘0’ consecutive reduce the gain forthese stages in some little step, and if there is not N2 ‘1’s or ‘0’consecutive increase the gain for these stages in some little step. Theprocess is repeated until the gain is in its desired range. In anexemplary embodiment, the output bits are monitored continuously duringthe operation of the sampler and the identification process is repeatedas necessary. The values for N1, N2 depends on how close it is desiredto be to instability, and a good value is around N1=4, N2=3. The justdescribed algorithm is based on the observation that a sequence of samevalue ‘111 . . . ’ or ‘000 . . . ’ in the binary vector v representingthe input sample (while ignoring the ISI since assuming it issufficiently low) is not possible during stable operation. A sequence ofsame value indicating that the residual (i.e. the signal that is passedfrom stage to stage) is repeatedly tried to be controlled in each stage,but each time the residual multiplied by the gain of the stage is largerthan the compensation. This is indicating that the gain is too high andinstability is highly probable. In the other direction, a gain too lowdoes not make it possible to have few bits of the same value since thecorrection is soon changing the sign of the residual.

There is DSP 53 reconstructing digital output signal 59 using digitalrepresentation of the discrete correction signals (78,79) and theidentified model of sampler 75, wherein digital output signal 59represents the analog input signal 54.

DSP 53 is reconstructing digital output 59 (that represents the analoginput signal 54) using digital representation of the discrete correctionsignals (78,79) and the model of sampler 75 representing therelationships between digital representation of the discrete correctionsignals (78,79) to analog input signal 54. For example, in the linearcase disclosed above, the input signal is reconstructed by:x(i)=trace(C′V)+d

The maximum achievable accuracy and speed performance of any analogsignals sampler is limited by the non-ideal effects of its buildingblocks. Exemplary non-ideal effects are: settling time, finite amplifiergain, and/or analog component mismatch. When designing high-speed andhigh-accuracy analog signals sampler, just described non-ideal effectsimpose very stringent demands on the building blocks, leading toprolonged design time. Just described non-ideal effects also require theuse of manufacturing processes that are optimized for componentmatching, thus increasing the manufacturing cost. The exemplaryimplementation of the first multi-stage exemplary preferred embodimentof the generalized method and corresponding analog signals sampler ofthe present invention disclosed below relaxes aforementioneddesign-requirements.

In an exemplary implementation of the first multi-stage exemplarypreferred embodiment of the generalized method and corresponding analogsignals sampler of the present invention, an analog signal is passedthrough a series stages including MIMO and control systems, wherein eachstage is implemented as illustrated in FIG. 5. In each stage the signalis amplified, sampled, compared with a threshold and according to theresult of the comparison, a constant is subtracted or added to theamplified signal. In this exemplary implementation of the firstmulti-stage exemplary preferred embodiment, single ended implementationis used for clarity. In a practical implementation, a differentialcircuit is preferred.

In each stage, the input analog signal 54 is amplified by amplifier 80.In an exemplary embodiment of the present invention, amplifier 80 is atransconductance amplifier (converts voltage input to current output).In an exemplary embodiment of the present invention, the amplifiedanalog signal is approximately integrated by using capacitor 84 for theduration of switch 83 is closed. Switch 83 is closed during the lowportion of synchronization clock 56 (not shown in the figure). In analternative embodiment, amplifier 80 is switched off during the highportion of synchronization clock 56 (not shown in the figure) instead ofusing switch 83. Resistor 85 is used to discharge capacitor 84 duringthe time switch 83 is open. The circuit is designed such that the timeconstant of the capacitor discharge is not too small, since during thattime constant the next stage is integrating. On the other hand, thecircuit is designed such that the time constant of the capacitordischarge is not too long, so that the capacitor is mostly discharged atthe end of the time constant. The residual voltage is summed with thenext sample and is causing Inter Symbol Interference (ISI). This ISI isnot desired but usually is not reducing the performance of the samplersince it can modeled and corrected for in the DSP 53.

Controller 68 is comparing the analog signal with a threshold. Wheneverthe result of the comparison is positive, a constant K is subtracted atvoltage adder 81 by using selector 86. Otherwise, a constant K 86 isadded at voltage adder 81. The subtraction or addition are effectiveduring the high period of clock 56, or for constant part of the highperiod of clock 56 (for example, the second half of the high period),when the comparator is assumed to be stable. Each comparison decisionprovides one bit to the representation of the analog signal and storedin digital logic 87. Digital logic 87 is holding the value in itsdigital input until a new rising edge of synchronization clock 56 isreceived. Digital logic 87 is adapted to register the output ofcomparator 82. Digital logic 87 is sampling its digital input at the endof the high period of synchronization clock 56 when the output ofcomparator 82 is stable. In an exemplary embodiment, the threshold valueused by comparator 82 is zero and digital logic 87 is a D-flip-floptype. The result of the amplification, integration, discharge and theintegration in the next stage results in an amplification of the signalwhen passing from stage to stage. That amplifying factor is denoted by‘alfa’. alfa featuring a value in the interval of 1<alfa<2. alfafeaturing a value of more than 2 causes the sampler to diverge. alfafeaturing a value of less then 1 is not useful since the analog signalis not amplified. Neither the value of gain alfa nor the value ofconstant K need to be accurate since they are estimated by DSP 53.

Comparator 82 is controlling the value of the voltages that is added bythe voltage adder 81 to the sampled signal. In an exemplary embodiment,the comparator is controlling a switch. The switch is choosing betweentwo constants such as K and −K or K1 and K2 with the raising ofsynchronization clock 56. In an alternative exemplary embodiment, thecomparator can either subtract a constant or do nothing.

Herein disclosed an operational example of two stages, illustrating themulti-stage analog signal sampler operation. During the low portion ofsynchronization clock 56, switch 83 is closed (or alternatively,amplifier 80 is switched on), capacitor 84 is charged with the amplifiercurrent less the current that is wasted into resistor 85. At the risingedge of synchronization clock 56, comparator 82 is activated andmeasuring the polarity of the signal on capacitor 84. Comparator 82 iscontrolling the correction (K or −K in switch 86) that is added to thevoltage during the second half period of synchronization clock 56. Inthat second half period of synchronization clock 56, the following stageis active. In other words, the activating timing of the amplifier andcomparator of the following stage is opposite in respect to itspreceding stage. During the time that the current stage is inactive,capacitor 84 is discharged close to zero to be prepared for the nextsample. During that time, the amplifier of the following stage is usingvoltage 76 and the capacitor of the following stage is integrating. Theamplifier of the following stage features extra gain in order tocompensate for the decreasing voltage 76 during the integration in thecapacitor of the following stage.

In an alternative exemplary embodiment of the present invention, insteadof generating and adding voltage as illustrated in FIG. 5, currents aregenerated and added as illustrated in FIG. 6. Currents are addeddirectly at adder 90 and amplifier 89 is only a driving amplifier anddoes not belong to first stage 67. Except for the different circuitconnections, the two exemplary embodiments illustrated in FIG. 5 andFIG. 6 are mathematically equivalent.

Herein described the second multi-stage exemplary preferred embodimentof the generalized method and corresponding analog signals sampler ofthe present invention. The second multi-stage exemplary preferredembodiment, as illustrated in FIG. 7, relates to a similar parallelmulti-stage type embodiment of the sampler disclosed above in the firstmulti-stage exemplary preferred embodiment of the generalized method andcorresponding analog signals sampler of the present invention. Theparallel multi-stage type embodiment featuring enhances performance whendealing with external noise source. The parallel multi-stage typeembodiment including a plurality of samplers featuring a plurality ofstages, wherein each stage, features MIMO system and controller (67A,70A, 68A, 71A, 67B, 70B, 68B, 71B), producing an analog monitoringoutput (76A, 77A, 76B, 77B) and digital representation of the discretecorrection signals (78A, 79A, 78B, 79B). A digital representation ofanalog input signal 59′ can be obtained from the identified model of thesamplers and the digital representation of the discrete correctionsignals produced by each stage of each sampler.

Referring to FIG. 7 compared with FIG. 4, the exemplary parallelmulti-stage embodiment features two multi-stage samplers (75A and 75B),wherein these two multi-stage samplers are sampling the same analoginput signal 54. Each one of these two multi-stage samplers (75A and75B), is implemented, with the required changes, in accordance with themethod and corresponding device of the first multi-stage exemplarypreferred embodiment described above and may incorporate all disclosedfeatures and alternative exemplary embodiments.

In an alternative embodiment of the parallel multi-stage type, theplurality of parallel analog signal samplers are sampling at least twodifferent analog signals. In this parallel multi-stage type embodiment,the plurality of parallel analog signal samplers are placed on the samesilicon substrate, featuring crosstalk between the plurality of analogsignal samplers, resulting in one system requiring a common signalprocessing. The common signal processing enables eliminating thecrosstalk effect or decreasing its negative influence.

It is to be understood that FIG. 7 is illustrates schematically aparallel multi-stage sampler including two multi-stage samplers 75A and75B, each one includes two stages 73 and 74. The parallel multi-stagesampler in accordance with the present invention can be scaled throughduplications of its multi-stage samplers 75A and/or 75B or duplicationsof stages 73 and/or 74 within each multi-stage sampler, as is well knownin the art of electronic hardware design.

The exemplary parallel multi-stage type embodiment, as illustrated inFIG. 7, enhances the performance of the sampler of the present inventionin an environment featuring external noise source. An example for suchan external noise source is noise on a power supply.

The two multi-stage samplers (75A and 75B) usually feature a crosstalkeffect since they are closed by. In an exemplary embodiment of thepresent invention, the two multi-stage samplers are treated as oneunified sampler with twice as many output bits or more, depending on thechosen multiplicity. It is assumed that an external noise source isentering all the multi-stage samplers, but due to different analog pathlength, the external noise source is affecting differently eachmulti-stage sampler. Therefore, there should be two or morerepresentations of the same analog input signal, each representationfeatures different added external noise. DSP 53′ can cancel the addedexternal noise whenever the added external noise is correlated. Forexample,y1=x+n·b1, y2=x+n·b2are two outputs, where x is an input signal, n is an added externalnoise source, and b1,b2 are coefficients. The equations are solved for nusing (y2−y1)/(b2−b1). It is understood that having two outputs andcorrelated added external noise enable calculating the added externalnoise, and thereby cancel that calculated added external noise.Moreover, it is understood that b1 must not be equal to b2 in order toenable this example. In the physical world, b1 should not be equal to b2due to the randomness in the layout of the circuit, otherwise, it ispossible to design the two or more multi-stage samplers slightlydifferent in order to ensure that the add external noise is not enteringwith the same coefficients. Additionally, it is to be understood thatthere is a need for using plurality of weighting coefficients andplurality of samples of the added external noise over time since thesystem is not memoryless, and just for the purpose of simplifying andclearly explaining the example it is expressed with a single sample.

Thus, it is understood from the embodiments of the invention hereindescribed and illustrated, above, that the method and correspondingdevice for sampling analog signals and providing digital representationthereof, of the present invention, are novel and neither anticipated orobviously derived from the previous art.

Moreover, implementation of the present invention results insignificantly increasing the throughput, reducing consumed power, andincreasing resolution of known in the art analog signals samplers.

It is appreciated that certain features of the invention, which are, forclarity, described in the context of separate embodiments, may also beprovided in combination in a single embodiment. Conversely, variousfeatures of the invention, which are, for brevity, described in thecontext of a single embodiment, may also be provided separately or inany suitable sub-combination.

It is to be understood that the present invention is not limited in itsapplication to the details of the order or sequence of functions ofoperation, or operations, or implementation of the method for samplinganalog signals and providing digital representation thereof or to thedetails of construction, arrangement, and, composition of thecorresponding analog signals sampler thereof, set in the description,drawings, or examples of the present invention.

All publications, patents and patent applications mentioned in thisspecification are herein incorporated in their entirety by referenceinto the specification, to the same extent as if each individualpublication, patent or patent application was specifically andindividually indicated to be incorporated herein by reference. Inaddition, citation or identification of any reference in thisapplication shall not be construed as an admission that such referenceis available as prior art to the present invention.

While the invention has been described in conjunction with specificembodiments and examples thereof, it is evident that many alternatives,modifications and variations will be apparent to those skilled in theart. Accordingly, it is intended to embrace all such alternatives,modifications and variations that fall within the spirit and broad scopeof the appended claims.

1. A method for providing a digital output signal representing at leastone analog input signal, comprising: (a) feeding an analog circuit withsaid at least one analog input signal and a plurality of discretecorrection signals; (b) said analog circuit providing analog monitoringoutputs, wherein said at least one analog input signal and said discretecorrection signals are jointly related by a relationship to said analogmonitoring outputs, said relationship having an identificationalgorithm; (c) receiving said analog monitoring outputs and asynchronization clock and implementing a negative feedback control loopby said feeding said analog circuit with said discrete correctionsignals, in order to keep at least one of said analog monitoring outputsto be within a previously defined constraint; (d) identifying saidrelationship thereby creating an internal representation of saidrelationship; (e) calculating said digital output signal by using adigital representation of said discrete correction signals and saidinternal representation, wherein said digital output signal representssaid at least one analog input signal.
 2. The method of claim 1, furthercomprising the step of, prior to said (a) feeding: (f) training byinputting a plurality of known analog training signals into said analogcircuit.
 3. The method of claim 1, wherein said analog circuit is timevarying according to said synchronization clock.
 4. The method of claim1, wherein said discrete correction signals are based on selectablyeither at least two previously defined values or at least two previouslydefined waveforms.
 5. The method of claim 1, wherein said analog circuitis a linear analog circuit.
 6. The method of claim 5 wherein saididentifying includes a least-mean square (LMS) technique.
 7. The methodof claim 1, wherein said calculating is only up to a previously definedpartial reconstruction of said at least one analog input signal.
 8. Themethod of claim 1, wherein said identifying is repeated occasionallywithin a training period, and said identifying includes feeding at leastone analog training signal during said training period.
 9. The method ofclaim 8, wherein said at least one analog signal is produced by feedingknown digital signals to a digital to analog converter, said knowndigital signals driving said at least one analog training signal. 10.The method of claim 8, where said identifying is performed in thebackground by interleaving said at least one analog input signal andsaid at least one analog training signal.
 11. The method of claim 8,wherein said at least one analog training signal is produced bycascading said analog circuit with at least one additional analogcircuit fed by a known reference signal and said identifying is of arelationship between said known reference signal and an output of saidanalog circuit.
 12. The method of claim 1, wherein said identifying usesavailable statistical information about said at least one analog inputsignal.
 13. The method of claim 1, wherein said analog circuit is amulti-stage analog circuit including a plurality of stages, the methodfurther comprising the steps of: (a) for each said stage, except thefirst stage, receiving as input signals at least one analog signal froma preceding stage and at least one discrete correction signal; (b) thefirst stage receiving as inputs at least one discrete correction signaland at least one analog input signal; (c) for each said stage, providingat least one analog monitoring output, (d) providing, for each stage ofthe multi-stage analog circuit, said at least one discrete correctionsignal.
 14. The method of claim 13, wherein operation of each stage isdependent on at least one other stage.
 15. The method of claim 1,wherein at least one of said analog monitoring outputs is timecontinuous.
 16. A multi-stage analog signals sampler, wherein each stageof the multi-stage analog signals sampler includes: (a) an amplifierwhich amplifies an input analog signal, thereby producing an amplifiedanalog signal; (b) a capacitor which at least approximately integratessaid amplified analog signal, thereby producing an integrated signal;wherein a discharge mechanism discharges said capacitor; and (c) amechanism which performs a comparison of said integrated signal with atleast one threshold, and adds at least one previously defined correctionto said amplified analog signal, and registers an output of saidcomparison in a digital logic.
 17. A multi-stage analog signals sampler,wherein each stage of said multi-stage analog signals sampler includes:(a) an amplifier amplifying an analog input signal, thereby producing anamplified analog signal; (b) a mechanism which renders said amplifierdependent on a synchronization clock; (c) a circuit which features atime constant on the order of a period of said synchronization clock,wherein said circuit modifies said amplified analog signal; (d) amechanism which provides, at least one discrete correction signal tosaid analog input signal, by using information from at least one othersaid stage, wherein said at least one discrete correction signalperforms a negative feedback control loop which controls said analoginput signal; and (e) a mechanism which receives and stores, a digitalrepresentation of said at least one discrete correction signal.
 18. Themulti-stage analog signals sampler, according to claim 17, furthercomprising (f) a mechanism which identifies a relationship between saidat least one discrete correction signal, said analog input signal andsaid information used in said negative feedback control loop of saidmulti-stage analog signals sampler, (g) a digital signal processingmechanism which calculates a digital output signal representing saidanalog input signal.
 19. A parallel analog signals sampler, comprising aplurality of the multi-stage analog signals samplers according to claim17, wherein the respective digital representations of the multi-stagesignal samplers are output to a common digital signal processingmechanism, the parallel analog signals sampler comprising a mechanismwhich identifies a joint relationship between a parallel input and theparallel output of said multi-stage analog signals samplers.
 20. Theparallel multi-stage analog signals sampler, according to claim 19,wherein said multi-stage analog signals samplers are placed in closeproximity, wherein crosstalk between said parallel analog signalsamplers is included in said joint model.